In testing a semiconductor device by a semiconductor test system, test patterns with various timings must be applied to the semiconductor device under test. The timing resolution and accuracy must be very high, such as 1/100 of a time period of a reference clock in the semiconductor test system. This invention is directed to a delay circuit for producing a high resolution delay time, although the application of the invention is not limited to semiconductor test systems.
An example of a conventional delay circuit for such a purpose is shown in FIGS. 3-6. As shown in FIG. 5, the delay circuit includes a coarse delay circuit 20, a conversion memory 31, a flip-flop 50, an AND gate 11, and a fine delay circuit 61. The delay circuit of FIG. 5 is to produce a delayed signal q at the output of the fine delay circuit 61 which is delayed by a predetermined time from a start signal b with use of a reference clock a.
The coarse delay circuit 20 is to produce a pulse signal whose delay time is integer multiple of one clock cycle (time period) of the reference clock a by counting the number of pulses of the reference clock a. In the example of FIG. 5, the coarse delay circuit 20 includes a start/stop control circuit 21, a memory 22 and a down counter 23. The start/stop control circuit 21 is provided with the start signal b and the reference clock a. The down counter 23 generates a delayed pulse (borrow signal) m which is provided to the flip-flop 50.
The fine delay circuit 61 is to add a fractional delay time which is smaller than the one cycle of the reference clock a to the delayed pulse m having a delay time which is integer multiple of the reference clock cycle from the coarse delay circuit 20. Consequently, the delayed signal q having a high resolution timing delay is produced at the output of the fine delay circuit 61. As shown in FIG. 3, the fine delay circuit 61 includes series connected small time delay circuits 5a, 5b, . . . 5n having different fractional delay times from one another. Each of the small time delay circuits 5a-5n has both a delay path for supplying a fractional delay time to an incoming signal and a through path for not supplying the fractional delay time.
The fractional delay time in the delay path is produced by a series connected delay elements 1a-1n which are formed, for example of CMOS buffers or gates. Either one of the delay path or the through path in the small time delay circuit is selected by an output of a flip-flop 4 which is controlled by a select signal t (digital codes from the conversion memory 31). An output signal F through the selected path is generated at the output of an OR gate 3 to be supplied to the next stage of the small time delay circuit 5b as shown in FIG. 3.
The operation of the delay circuit of FIG. 5 is explained with reference to the timing chart of FIG. 6. In this example, a pulse signal which is delayed by 202.5 ns relative to the start signal b is produced by the delay circuit of FIG. 5 wherein one cycle time of the reference clock is 100 ns. Further, for simplicity of explanation, the timing chart of FIG. 6 does not include a propagation delay time of each component in the delay circuit.
In the coarse delay circuit 20, the start signal b (FIG. 6A) which is synchronized with the reference clock a (FIG. 6B) is provided to the start/stop control circuit 21. The reference clock a is also provided to a clock terminal of the start/stop control circuit 21. The start signal b enables the reference clock a to pass through the start/stop control circuit 21. Thus, a clock signal k (FIG. 6C) having the same clock rate as the reference clock a is supplied to the down counter 23.
The down counter 23 receives preset data s from the memory 22 and counts the clock signal k defined by the preset data s. For example, the preset data s in this case indicates the ultimate delay timing 202.5 ns that is the delay time desired to be produced by the delay circuit of FIG. 5. Based on the higher bits of the preset data s, the down counter 23 generates a borrow signal (terminal count) m when counting the predetermined number of the clock signal k defined by the higher bits of the preset data s. In the example of FIG. 6, since the higher bits indicates a delay time of 200 ns, the borrow signal m is generated at the third pulse (200 ns after the start signal b) of the clock signal k as shown in FIG. 6D.
The borrow signal m is provided to the flip-flop circuit 50 (FIG. 6E) and is re-timed at the AND gate 11 by the reference clock a. Thus, a delayed signal p having a 200ns delay time is produced at the output of the AND gate 11 as shown in FIG. 6F. The delayed signal p is provided to the fine delay circuit 61 for further receiving a fine (fractional) delay time T.sub.pd which is smaller than one cycle of the reference clock a as shown in FIG. 6G.
FIG. 4 is a timing chart showing an operation of the fine delay circuit of FIG. 3. For simplicity of explanation, the timing chart of FIG. 4 does not include a signal propagation delay time of each component in the delay circuit of FIG. 3. As noted above, the fine delay circuit 61 includes the series connected small time delay circuits 5a, 5b, . . . 5n having different fractional delay times from one another. Each of the small time delay circuits 5a-5n has the series connected delay elements 1a-1n such as CMOS gates to establish the fine delay time T.sub.pd. Either one of the delay path or the through path in the delay circuit is selected by controlling the output of the flip-flop 4 by the digital codes t.
Thus, when the output of the flip-flop 4 is as shown in FIG. 4C, the flip-flop 4 selects the delay path by opening the AND gate 2b. In the delay path, the delay time T.sub.pd produced by the delay elements 1a-1n is added to the input signal A of FIG. 4A to form a delayed signal c shown in FIG. 4B. Thus, the output of the small time delay circuit 5a provides the delayed signal F (FIG. 4D) to the next small time delay circuit 5b.In this manner, the fractional delay time T.sub.pd which is smaller than the reference clock cycle is added to the input signal by the fine delay circuit 61.
Typically, the small time delay circuits 5a-5n have different number of the delay elements to establish the different fractional delay times T.sub.pd from the other. To produce a longer delay time, a larger number of delay elements 1a-1n must be assigned in the delay circuit 61. By selecting one or more small time delay circuits, a desired fine delay time which is smaller than the one reference clock cycle can be produced.
For example, the small time delay circuit 5a has a delay time which is a half (1/2) of the one cycle of the reference clock a. The delay circuit 5b has a delay time which is a half of that of the delay circuit 5a. Similarly, the delay circuit 5c has a delay time which is a half of that of the delay circuit 5b, and the delay circuit 5d has a delay time which is a half of that of the delay circuit 5c, and so on. Thus, in case where one cycle of the reference clock a is 100 ns and the intended timing resolution is 0.1 ns, the fine delay circuit 61 will be formed of ten (10) small time delay circuits 5 having delay times of 50 ns, 25 ns, 12.5 ns, 6.3 ns, 3.2 ns, 1.6 ns, 0.8 ns, 0.4 ns, 0.2 ns, and 0.1 ns, respectively.
The digital codes t for controlling the small time delay circuits 5a-5n are provided by the conversion memory 31. The digital codes are produced by the conversion memory 31 by reading digital data r in the memory 22 in the coarse delay circuit 20. In the above example of generating the delay time of 202.5 ns, the fine delay circuit 61 must provides a delay time of 2.5 ns to the incoming signal. Thus, the small time delay circuits 5 of 1.6 ns, 0.8 ns and 0.1 ns are respectively selected by the digital codes. Therefore, in FIG. 5, the 200 ns delayed signal P at the input of the fine delay circuit 61 is provided with the delay time of 2.5 ns to establish the intended delay time of 202.5ns.
In the conventional delay circuit of FIGS. 3-6, the fractional delay times T.sub.pd in the small time delay circuits 5a-5n are dependent upon the time period of the reference clock. If the time period of the reference clock is increased, the fine delay circuit 61 to cover the delay times smaller than one cycle period of the reference clock must have capability of adjusting longer delay times corresponding to the reference clock. Consequently, the number of delay elements such as CMOS gates in the fine delay circuit must be increased. Not only increasing the number of components, but the longer delay time also decreases the timing accuracy and resolution. Further, the capacity of the memory 31 must also be increased since the digital codes to control the fine delay circuits need to have larger bits.
In case where the time period of the reference clock is shortened, i.e., the frequency of the reference clock is increased, electric power consumption by the CMOS gate forming the delay elements will increase. The increase of the power consumption in the delay circuit also causes thermal noise to a signal propagating therethrough. Further, such an increase in the frequency of the reference clock is limited by the operational speed of the coarse delay circuit 20. Moreover, the increase in the operational speed in the delay circuit requires high cost circuit components.